Only in nuttx-6.22: Make.defs Only in nuttx-6.22/arch/arm/include: board Only in nuttx-6.22/arch/arm/include: chip Only in nuttx-6.22/arch/arm/src: board Only in nuttx-6.22/arch/arm/src: chip diff -ur nuttx-6.22.orig/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h nuttx-6.22/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h --- nuttx-6.22.orig/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h 2012-09-30 04:16:02.000000000 +0900 +++ nuttx-6.22/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h 2012-10-27 18:18:20.000000000 +0900 @@ -222,7 +222,7 @@ #define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) #define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) #define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) #define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) #define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) diff -ur nuttx-6.22.orig/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h nuttx-6.22/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h --- nuttx-6.22.orig/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h 2012-09-30 04:16:02.000000000 +0900 +++ nuttx-6.22/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h 2012-10-27 18:18:08.000000000 +0900 @@ -222,7 +222,7 @@ #define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) #define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) #define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) #define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) #define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) diff -ur nuttx-6.22.orig/arch/arm/src/stm32/stm32_eth.c nuttx-6.22/arch/arm/src/stm32/stm32_eth.c --- nuttx-6.22.orig/arch/arm/src/stm32/stm32_eth.c 2012-09-30 04:16:02.000000000 +0900 +++ nuttx-6.22/arch/arm/src/stm32/stm32_eth.c 2012-10-28 20:18:36.000000000 +0900 @@ -667,6 +667,9 @@ #ifdef CONFIG_PHY_DM9161 static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv); #endif +#ifdef CONFIG_PHY_LAN8720 +static inline int stm32_lan8720(FAR struct stm32_ethmac_s *priv); +#endif /* CONFIG_PHY_LAN8720 */ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv); /* MAC/DMA Initialization */ @@ -2549,6 +2552,55 @@ #endif /**************************************************************************** + * Function: stm32_lan8720 + * + * Description: + * Special workaround for the SMSC LAN8720A PHY is required. On power, + * up, the PHY is not usually configured correctly but will work after + * a powered-up reset. This is really a workaround for some more + * fundamental issue with the PHY clocking initialization, but the + * root cause has not been studied (nor will it be with this workaround). + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PHY_LAN8720 +static inline int stm32_lan8720(FAR struct stm32_ethmac_s *priv) +{ + uint16_t phyval; + int ret; + + /* Read the PHYID1 register; A failure to read the PHY ID is one + * indication that check if the LAN8720A PHY CHIP is not ready. + */ + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); + if (ret < 0) + { + ndbg("Failed to read the PHY ID1: %d\n", ret); + return ret; + } + + /* If we failed to read the PHY ID1 register, the reset the MCU to recover */ + + else if (phyval == 0xffff) + { + up_systemreset(); + } + + nvdbg("PHY ID1: 0x%04X\n", phyval); + + return OK; +} +#endif /* CONFIG_PHY_LAN8720 */ + + +/**************************************************************************** * Function: stm32_phyinit * * Description: @@ -2603,6 +2655,14 @@ } #endif +#ifdef CONFIG_PHY_LAN8720 + ret = stm32_lan8720(priv); + if (ret < 0) + { + return ret; + } +#endif /* CONFIG_PHY_LAN8720 */ + /* Perform auto-negotion if so configured */ #ifdef CONFIG_STM32_AUTONEG @@ -3369,6 +3429,12 @@ /* Register the device with the OS so that socket IOCTLs can be performed */ + priv->dev.d_mac.ether_addr_octet[0]=CONFIG_STM32_ETHMAC_ADDR_OCTET_0; + priv->dev.d_mac.ether_addr_octet[1]=CONFIG_STM32_ETHMAC_ADDR_OCTET_1; + priv->dev.d_mac.ether_addr_octet[2]=CONFIG_STM32_ETHMAC_ADDR_OCTET_2; + priv->dev.d_mac.ether_addr_octet[3]=CONFIG_STM32_ETHMAC_ADDR_OCTET_3; + priv->dev.d_mac.ether_addr_octet[4]=CONFIG_STM32_ETHMAC_ADDR_OCTET_4; + priv->dev.d_mac.ether_addr_octet[5]=CONFIG_STM32_ETHMAC_ADDR_OCTET_5; (void)netdev_register(&priv->dev); return OK; } diff -ur nuttx-6.22.orig/configs/stm32f4discovery/include/board.h nuttx-6.22/configs/stm32f4discovery/include/board.h --- nuttx-6.22.orig/configs/stm32f4discovery/include/board.h 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/include/board.h 2012-10-28 14:22:44.000000000 +0900 @@ -157,6 +157,61 @@ #define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY #define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY +/* SDIO *****************************************************************************/ +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channl/Stream Selections *****************************************************/ +/* Stream selections are arbitrary for now but might become important in the future + * is we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Ethernet *************************************************************************/ +/* RMII LAN8270A */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) +# if !defined(CONFIG_STM32_RMII) +# warning "CONFIG_STM32_RMII required for Ethernet" +# else +# define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1 // PB11 +# define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1 // PB12 +# define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 // PB13 +# define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_2 // PG8 PPS_OUT is allocated dummy pin +# endif +#endif + /* LED definitions ******************************************************************/ /* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any * way. The following definitions are used to access individual LEDs. @@ -213,9 +268,14 @@ * (See the README.txt file for other options) */ +// serial console PA2=TX2,PA3=RX2 #define GPIO_USART2_RX GPIO_USART2_RX_1 #define GPIO_USART2_TX GPIO_USART2_TX_1 +// serial console PD8=TX3,PD9=RX3 +#define GPIO_USART3_RX GPIO_USART3_RX_3 +#define GPIO_USART3_TX GPIO_USART3_TX_3 + /* PWM * * The STM32F4 Discovery has no real on-board PWM devices, but the board can be @@ -224,12 +284,19 @@ #define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 +// piezzo buzzer PB8=TIM10_1 +#define GPIO_TIM10_CH1OUT GPIO_TIM10_CH1OUT_1 + /* SPI */ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 #define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 +#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 // PB14 +#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 // PB15 +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1 // PB10 + /* Timer Inputs/Outputs (see the README.txt file for options) */ #define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2 @@ -238,6 +305,12 @@ #define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1 #define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1 +// on board LEDs w/PWM (caution: nuttx status indication used) +#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_2 +#define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 +#define GPIO_TIM4_CH3OUT GPIO_TIM4_CH3OUT_2 +#define GPIO_TIM4_CH4OUT GPIO_TIM4_CH4OUT_2 + /************************************************************************************ * Public Data ************************************************************************************/ diff -ur nuttx-6.22.orig/configs/stm32f4discovery/nsh/Make.defs nuttx-6.22/configs/stm32f4discovery/nsh/Make.defs --- nuttx-6.22.orig/configs/stm32f4discovery/nsh/Make.defs 2012-09-30 04:14:50.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/nsh/Make.defs 2012-10-27 10:02:56.000000000 +0900 @@ -90,9 +90,15 @@ endif ifeq ($(CONFIG_STM32_BUILDROOT),y) # NuttX buildroot under Linux or Cygwin - CROSSDEV = arm-elf- - ARCROSSDEV = arm-elf- - ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + # CROSSDEV = arm-elf- + # ARCROSSDEV = arm-elf- + # ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + # CROSSDEV = arm-none-eabi- + # ARCROSSDEV = arm-none-eabi- + # ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + CROSSDEV = arm-hardfloat-eabi- + ARCROSSDEV = arm-hardfloat-eabi- + ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fipa-sra MAXOPTIMIZATION = -Os endif diff -ur nuttx-6.22.orig/configs/stm32f4discovery/nsh/appconfig nuttx-6.22/configs/stm32f4discovery/nsh/appconfig --- nuttx-6.22.orig/configs/stm32f4discovery/nsh/appconfig 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/nsh/appconfig 2012-10-30 10:41:48.000000000 +0900 @@ -36,6 +36,12 @@ # Path to example in apps/examples containing the user_start entry point CONFIGURED_APPS += examples/nsh +CONFIGURED_APPS += netutils/uiplib +CONFIGURED_APPS += netutils/resolv +CONFIGURED_APPS += netutils/telnetd +CONFIGURED_APPS += netutils/tftpc +CONFIGURED_APPS += netutils/webclient + # The NSH application library @@ -65,3 +71,8 @@ ifeq ($(CONFIG_WATCHDOG),y) CONFIGURED_APPS += examples/watchdog endif + +ifeq ($(CONFIG_EXAMPLES_OSTEST_BUILTIN),y) +CONFIGURED_APPS += examples/ostest +endif + diff -ur nuttx-6.22.orig/configs/stm32f4discovery/nsh/defconfig nuttx-6.22/configs/stm32f4discovery/nsh/defconfig --- nuttx-6.22.orig/configs/stm32f4discovery/nsh/defconfig 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/nsh/defconfig 2012-10-31 21:16:34.000000000 +0900 @@ -44,27 +44,35 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_DRAM_SIZE=196608 +#CONFIG_DRAM_SIZE=0x0001c000 +#CONFIG_DRAM_SIZE=0x00030000 CONFIG_DRAM_START=0x20000000 CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_FPU=n -CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_INTERRUPTSTACK=n CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_BOOTLOADER=n CONFIG_ARCH_LEDS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +CONFIG_ARCH_DMA=y + +CONFIG_ARCH_FPU=y +CONFIG_ARMV7M_CMNVECTOR=n + +#CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_CCMEXCLUDE=n +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n # # Identify toolchain and linker options # CONFIG_STM32_CODESOURCERYW=n -CONFIG_STM32_CODESOURCERYL=y +CONFIG_STM32_CODESOURCERYL=n CONFIG_STM32_ATOLLIC_LITE=n CONFIG_STM32_ATOLLIC_PRO=n CONFIG_STM32_DEVKITARM=n CONFIG_STM32_RAISONANCE=n -CONFIG_STM32_BUILDROOT=n +CONFIG_STM32_BUILDROOT=y # # JTAG Enable settings (by default only SW-DP is enabled): @@ -79,22 +87,22 @@ # # AHB1: CONFIG_STM32_CRC=n -CONFIG_STM32_BKPSRAM=n -CONFIG_STM32_CCMDATARAM=n -CONFIG_STM32_DMA1=n -CONFIG_STM32_DMA2=n -CONFIG_STM32_ETHMAC=n +CONFIG_STM32_BKPSRAM=y +CONFIG_STM32_CCMDATARAM=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y CONFIG_STM32_OTGHS=n # AHB2: CONFIG_STM32_DCMI=n CONFIG_STM32_CRYP=n CONFIG_STM32_HASH=n CONFIG_STM32_RNG=n -CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS=n # AHB3: CONFIG_STM32_FSMC=n # APB1: -CONFIG_STM32_TIM2=n +CONFIG_STM32_TIM2=y CONFIG_STM32_TIM3=n CONFIG_STM32_TIM4=n CONFIG_STM32_TIM5=n @@ -107,8 +115,8 @@ CONFIG_STM32_IWDG=n CONFIG_STM32_SPI2=n CONFIG_STM32_SPI3=n -CONFIG_STM32_USART2=y -CONFIG_STM32_USART3=n +CONFIG_STM32_USART2=n +CONFIG_STM32_USART3=y CONFIG_STM32_UART4=n CONFIG_STM32_UART5=n CONFIG_STM32_I2C1=n @@ -125,20 +133,20 @@ CONFIG_STM32_USART6=n CONFIG_STM32_ADC1=n CONFIG_STM32_ADC2=n -CONFIG_STM32_ADC3=n -CONFIG_STM32_SDIO=n -CONFIG_STM32_SPI1=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=n CONFIG_STM32_SYSCFG=y -CONFIG_STM32_TIM9=n -CONFIG_STM32_TIM10=n +CONFIG_STM32_TIM9=y +CONFIG_STM32_TIM10=y CONFIG_STM32_TIM11=n # # STM32F40xxx specific serial device driver settings # CONFIG_USART1_SERIAL_CONSOLE=n -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART3_SERIAL_CONSOLE=n +CONFIG_USART2_SERIAL_CONSOLE=n +CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_UART4_SERIAL_CONSOLE=n CONFIG_UART5_SERIAL_CONSOLE=n @@ -197,14 +205,15 @@ # # STM32F40xxx Ethernet device driver settings # -CONFIG_STM32_PHYADDR=1 -CONFIG_STM32_MII=y -CONFIG_STM32_MII_MCO1=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_MII=n +CONFIG_STM32_MII_MCO1=n CONFIG_STM32_MII_MCO2=n -CONFIG_STM32_RMII=n +CONFIG_STM32_RMII=y +CONFIG_STM32_RMII_EXTCLK=y CONFIG_STM32_AUTONEG=y -#CONFIG_STM32_ETHFD -#CONFIG_STM32_ETH100MB +CONFIG_STM32_ETHFD=y +CONFIG_STM32_ETH100MB=y CONFIG_STM32_PHYSR=16 CONFIG_STM32_PHYSR_SPEED=0x0002 CONFIG_STM32_PHYSR_100MBPS=0x0000 @@ -213,15 +222,12 @@ CONFIG_STM32_ETH_PTP=n CONFIG_STM32_ETHMAC_REGDEBUG=n -# -# PWM configuration -# -# The stm32f4discovery has no real on-board PWM devices, but the board can be configured to output -# a pulse train using TIM4 CH2. (Don't forget to set CONFIG_STM32_TIM4=y above) -# -CONFIG_PWM=n -CONFIG_STM32_TIM4_PWM=y -CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_ETHMAC_ADDR_OCTET_0=0x02 +CONFIG_STM32_ETHMAC_ADDR_OCTET_1=0x03 +CONFIG_STM32_ETHMAC_ADDR_OCTET_2=0x04 +CONFIG_STM32_ETHMAC_ADDR_OCTET_3=0x05 +CONFIG_STM32_ETHMAC_ADDR_OCTET_4=0x00 +CONFIG_STM32_ETHMAC_ADDR_OCTET_5=0x01 # # Quadrature Encoder configuration. @@ -238,7 +244,7 @@ CONFIG_RRLOAD_BINARY=n CONFIG_INTELHEX_BINARY=y CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y +CONFIG_RAW_BINARY=n CONFIG_HAVE_LIBM=n # @@ -246,9 +252,9 @@ # CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_FS=n +CONFIG_DEBUG_VERBOSE=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_GRAPHICS=n CONFIG_DEBUG_LCD=n CONFIG_DEBUG_USB=n @@ -257,6 +263,7 @@ CONFIG_DEBUG_ANALOG=n CONFIG_DEBUG_PWM=n CONFIG_DEBUG_CAN=n +CONFIG_DEBUG_SPI=n CONFIG_DEBUG_QENCODER=n CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -264,29 +271,46 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=0 -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 -CONFIG_GREGORIAN_TIME=n +CONFIG_TASK_NAME_SIZE=32 +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=11 +CONFIG_START_DAY=3 +CONFIG_GREGORIAN_TIME=y CONFIG_JULIAN_TIME=n +CONFIG_DEV_ZERO=y +CONFIG_DEV_NULL=y CONFIG_DEV_CONSOLE=y CONFIG_DEV_LOWCONSOLE=n CONFIG_MUTEX_TYPES=n CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 +CONFIG_SEM_PREALLOCHOLDERS=4 CONFIG_SEM_NNESTPRIO=0 CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +CONFIG_FDCLONE_STDIO=y CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WORKQUEUE=n +CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SCHED_WORKSTACKSIZE=2048 +CONFIG_SIG_SIGWORK=8 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n +CONFIG_NAMEDAPP=y +CONFIG_MSEC_PER_TICK=10 + +# +# System Logging +# + +CONFIG_SYSLOG=n +CONFIG_RAMLOG=n +CONFIG_RAMLOG_CONSOLE=n +CONFIG_RAMLOG_SYSLOG=y +#CONFIG_RAMLOG_NPOLLWAITERS +CONFIG_RAMLOG_CONSOLE_BUFSIZE=32768 + + # # Settings for NXFLAT # @@ -343,20 +367,20 @@ # # Sizes of configurable things (0 disables) # -CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=4 -CONFIG_NPTHREAD_KEYS=4 +CONFIG_MAX_TASKS=32 +CONFIG_MAX_TASK_ARGS=8 +CONFIG_NPTHREAD_KEYS=8 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 CONFIG_STDIO_BUFFER_SIZE=256 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_PREALLOC_MQ_MSGS=16 +CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_PREALLOC_TIMERS=16 # # Framebuffer driver options @@ -370,18 +394,20 @@ # # Filesystem configuration # -CONFIG_FS_FAT=n +CONFIG_FS_FAT=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 CONFIG_FS_NXFFS=n CONFIG_FS_ROMFS=n +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y # # SPI-based MMC/SD driver # -CONFIG_MMCSD_NSLOTS=0 -CONFIG_MMCSD_READONLY=n +CONFIG_MMCSD_NSLOTS=1 +CONFIG_MMCSD_READONLY=y CONFIG_MMCSD_SPICLOCK=12500000 # @@ -393,10 +419,11 @@ # # STM32 SDIO-based MMC/SD driver # -CONFIG_SDIO_DMA=n +#CONFIG_SDIO_MUXBUS=n +#CONFIG_SDIO_DMA=y #CONFIG_SDIO_PRI=128 -#CONFIG_SDIO_DMAPRIO -#CONFIG_SDIO_WIDTH_D1_ONLY +#CONFIG_SDIO_DMAPRIO=8 +#CONFIG_SDIO_WIDTH_D1_ONLY=n CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_MMCSUPPORT=n CONFIG_MMCSD_HAVECARDDETECT=n @@ -404,7 +431,7 @@ # # TCP/IP and UDP support via uIP # -CONFIG_NET=n +CONFIG_NET=y CONFIG_NET_NOINTS=n CONFIG_NET_MULTIBUFFER=y CONFIG_NET_IPv6=n @@ -412,11 +439,11 @@ CONFIG_NET_SOCKOPTS=y CONFIG_NET_BUFSIZE=562 CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -#CONFIG_NET_TCP_READAHEAD_BUFSIZE +CONFIG_NET_TCP_CONNS=10 +CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 CONFIG_NET_TCPBACKLOG=y -CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_MAX_LISTENPORTS=10 CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y #CONFIG_NET_UDP_CONNS=10 @@ -425,21 +452,21 @@ #CONFIG_NET_PINGADDRCONF=0 CONFIG_NET_STATISTICS=y #CONFIG_NET_RECEIVE_WINDOW= -CONFIG_NET_BROADCAST=n -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_ARP_IPIN=n -CONFIG_NET_MULTICAST=n +CONFIG_NET_BROADCAST=y +CONFIG_NET_ARPTAB_SIZE=8 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_MULTICAST=y # # UIP Network Utilities # CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +CONFIG_NET_RESOLV_ENTRIES=8 # # RTC Configuration # -CONFIG_RTC=n +CONFIG_RTC=y CONFIG_RTC_DATETIME=y CONFIG_RTC_HIRES=n CONFIG_RTC_FREQUENCY=1 @@ -450,11 +477,11 @@ # CONFIG_USBDEV=n CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n +CONFIG_USBDEV_DUALSPEED=y CONFIG_USBDEV_SELFPOWERED=y CONFIG_USBDEV_REMOTEWAKEUP=n CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n +CONFIG_USBDEV_TRACE=y CONFIG_USBDEV_TRACE_NRECORDS=128 # @@ -579,8 +606,9 @@ # # Settings for examples/uip # -CONFIG_EXAMPLE_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLE_UIP_DRIPADDR=0x0a000001 +CONFIG_EXAMPLE_UIP_NOMAC=n +CONFIG_EXAMPLE_UIP_IPADDR=0xc0a801c9 +CONFIG_EXAMPLE_UIP_DRIPADDR=0xc0a80101 CONFIG_EXAMPLE_UIP_NETMASK=0xffffff00 CONFIG_EXAMPLE_UIP_DHCPC=n @@ -588,32 +616,25 @@ # Settings for examples/nettest CONFIG_EXAMPLE_NETTEST_SERVER=n CONFIG_EXAMPLE_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLE_NETTEST_NOMAC=y -CONFIG_EXAMPLE_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLE_NETTEST_DRIPADDR=0x0a000001 +CONFIG_EXAMPLE_NETTEST_NOMAC=n +CONFIG_EXAMPLE_NETTEST_IPADDR=0xc0a801c9 +CONFIG_EXAMPLE_NETTEST_DRIPADDR=0xc0a80101 CONFIG_EXAMPLE_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLE_NETTEST_CLIENTIP=0x0a000001 - -# -# Settings for examples/ostest -# -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLE_NETTEST_CLIENTIP=0xc0a80179 # # Settings for apps/nshlib # CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_STRERROR=y +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_NESTDEPTH=4 CONFIG_NSH_DISABLESCRIPT=n CONFIG_NSH_DISABLEBG=n CONFIG_NSH_ROMFSETC=n CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n +CONFIG_NSH_TELNET=y CONFIG_NSH_USBCONSOLE=n CONFIG_NSH_USBCONDEV="/dev/ttyACM0" CONFIG_NSH_UBSDEV_MINOR=0 @@ -623,12 +644,12 @@ CONFIG_NSH_USBDEV_TRACECONTROLLER=n CONFIG_NSH_USBDEV_TRACEINTERRUPTS=n #CONFIG_NSH_CONDEV -CONFIG_NSH_ARCHINIT=n +CONFIG_NSH_ARCHINIT=y CONFIG_NSH_IOBUFFER_SIZE=512 CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=y -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 +CONFIG_NSH_NOMAC=n +CONFIG_NSH_IPADDR=0xc0a801c9 +CONFIG_NSH_DRIPADDR=0xc0a80101 CONFIG_NSH_NETMASK=0xffffff00 CONFIG_NSH_ROMFSMOUNTPT="/etc" CONFIG_NSH_INITSCRIPT="init.d/rcS" @@ -642,10 +663,22 @@ # # Architecture-specific NSH options # -CONFIG_NSH_MMCSDSPIPORTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=2 CONFIG_NSH_MMCSDSLOTNO=0 CONFIG_NSH_MMCSDMINOR=0 +# Mount the SDIO-based MMC/SD block driver +CONFIG_NSH_HAVEMMCSD=y + +# +# Settings for examples/ostest +# +CONFIG_EXAMPLES_OSTEST_BUILTIN=y +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=4096 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 +CONFIG_EXAMPLES_OSTEST_FPUSIZE=(4*33) + # # Settings for examples/usbserial # @@ -675,14 +708,69 @@ # # Settings for examples/adc # +# CONFIG_ADC - Enabled ADC support +# CONFIG_NSH_BUILTIN_APPS - Build the ADC test as an NSH built-in function. +# Default: Built as a standalone problem +# +# CONFIG_EXAMPLES_ADC_DEVPATH - The path to the ADC device. Default: /dev/adc0 +# CONFIG_EXAMPLES_ADC_NSAMPLES - If CONFIG_NSH_BUILTIN_APPS +# is defined, then the number of samples is provided on the command line +# and this value is ignored. Otherwise, this number of samples is +# collected and the program terminates. Default: Samples are collected +# indefinitely. +# CONFIG_EXAMPLES_ADC_GROUPSIZE - The number of samples to read at once. +# Default: 4 +# +# (Don't forget to set CONFIG_STM32_TIM2=y above config lines) +# +CONFIG_ADC=n +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM2_ADC3=y +CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=1000000 +# CONFIG_STM32_ADCx_TIMTRIG Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO +CONFIG_STM32_ADC3_TIMTRIG=1 +CONFIG_ADC_DMA=n +# CONFIG_NSH_BUILTIN_APPS +# CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" +CONFIG_EXAMPLES_ADC_NSAMPLES=1 +# CONFIG_EXAMPLES_ADC_GROUPSIZE # # Settings for examples/can # + +# +# PWM configuration +# +# The stm32f4discovery has no real on-board PWM devices, but the board can be configured to output +# a pulse train using TIM4 CH2. (Don't forget to set CONFIG_STM32_TIM4=y above) +# +# changed for extention board for using TIM10_CH1 on PB8 +# (Don't forget to set CONFIG_STM32_TIM10=y above config lines) +# +CONFIG_STM32_TIM10_PWM=y +CONFIG_STM32_TIM10_CHANNEL=1 + # # Settings for examples/pwm # +# CONFIG_PWM - Enables PWM support. +# CONFIG_NSH_BUILTIN_APPS - Build the PWM test as an NSH built-in function. +# Default: Not built! The example can only be used as an NSH built-in +# application +# +# CONFIG_EXAMPLES_PWM_DEVPATH - The path to the PWM device. Default: /dev/pwm0 +# CONFIG_EXAMPLES_PWM_FREQUENCY - The initial PWM frequency. Default: 100 Hz +# CONFIG_EXAMPLES_PWM_DUTYPCT - The initial PWM duty as a percentage. Default: 50% +# CONFIG_EXAMPLES_PWM_DURATION - The initial PWM pulse train duration in sectonds. +# as a percentage. Default: 5 seconds + +CONFIG_PWM=y +CONFIG_EXAMPLES_PWM_BUILTIN=y +CONFIG_EXAMPLES_PWM_FREQUENCY=1000 +CONFIG_EXAMPLES_PWM_DUTYPCT=50 +CONFIG_EXAMPLES_PWM_DURATION=1 # # Settings for examples/watchdog @@ -706,8 +794,8 @@ CONFIG_BOOT_COPYTORAM=n CONFIG_CUSTOM_STACK=n CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= diff -ur nuttx-6.22.orig/configs/stm32f4discovery/scripts/ld.script nuttx-6.22/configs/stm32f4discovery/scripts/ld.script --- nuttx-6.22.orig/configs/stm32f4discovery/scripts/ld.script 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/scripts/ld.script 2012-10-30 19:51:56.000000000 +0900 @@ -53,7 +53,9 @@ } OUTPUT_ARCH(arm) -ENTRY(_stext) +/** ENTRY(_stext) **/ +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ SECTIONS { .text : { diff -ur nuttx-6.22.orig/configs/stm32f4discovery/src/Makefile nuttx-6.22/configs/stm32f4discovery/src/Makefile --- nuttx-6.22.orig/configs/stm32f4discovery/src/Makefile 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/src/Makefile 2012-10-30 20:33:22.000000000 +0900 @@ -60,6 +60,10 @@ CSRCS += up_usb.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += up_adc.c +endif + ifeq ($(CONFIG_PWM),y) CSRCS += up_pwm.c endif @@ -88,6 +92,10 @@ CSRCS += up_idle.c endif +ifeq ($(CONFIG_ARCH_FPU),y) +CSRCS += up_ostest.c +endif + ifeq ($(CONFIG_STM32_FSMC),y) CSRCS += up_extmem.c diff -ur nuttx-6.22.orig/configs/stm32f4discovery/src/stm32f4discovery-internal.h nuttx-6.22/configs/stm32f4discovery/src/stm32f4discovery-internal.h --- nuttx-6.22.orig/configs/stm32f4discovery/src/stm32f4discovery-internal.h 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/src/stm32f4discovery-internal.h 2012-10-28 14:24:58.000000000 +0900 @@ -86,10 +86,13 @@ * * The STM32F4 Discovery has no real on-board PWM devices, but the board can be * configured to output a pulse train using TIM4 CH2 on PD13. + * configured to output a pulse train using TIM10 CH1 on PB8 for ext-baseboard piezzo buzzer. */ -#define STM32F4DISCOVERY_PWMTIMER 4 -#define STM32F4DISCOVERY_PWMCHANNEL 2 +// #define STM32F4DISCOVERY_PWMTIMER 4 +// #define STM32F4DISCOVERY_PWMCHANNEL 2 +#define STM32F4DISCOVERY_PWMTIMER 10 +#define STM32F4DISCOVERY_PWMCHANNEL 1 /* SPI chip selects */ Only in nuttx-6.22/configs/stm32f4discovery/src: up_adc.c diff -ur nuttx-6.22.orig/configs/stm32f4discovery/src/up_nsh.c nuttx-6.22/configs/stm32f4discovery/src/up_nsh.c --- nuttx-6.22.orig/configs/stm32f4discovery/src/up_nsh.c 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/src/up_nsh.c 2012-10-31 14:14:54.000000000 +0900 @@ -45,6 +45,11 @@ #include #include +#ifdef CONFIG_STM32_SPI2 +# include +# include +#endif + #ifdef CONFIG_STM32_SDIO # include # include @@ -85,6 +90,47 @@ # undef HAVE_USBHOST #endif +/* For now, don't build in any SPI2 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI2 + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM32F4_DISCOVERY +# define CONFIG_NSH_HAVEUSBDEV 1 +# define CONFIG_NSH_HAVEMMCSD 1 +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#else + /* Add configuration for new STM32 boards here */ +# error "Unrecognized STM32 board" +# undef CONFIG_NSH_HAVEUSBDEV +# undef CONFIG_NSH_HAVEMMCSD +#endif + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef CONFIG_NSH_HAVEUSBDEV +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support + * is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef CONFIG_NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + /* Debug ********************************************************************/ #ifdef CONFIG_CPP_HAVE_VARARGS @@ -115,6 +161,15 @@ int nsh_archinitialize(void) { +#ifdef CONFIG_STM32_SPI2 + FAR struct spi_dev_s *spi; + FAR struct mtd_dev_s *mtd; +#endif +#ifdef CONFIG_NSH_HAVEMMCSD + FAR struct sdio_dev_s *sdio; + int ret; +#endif + #ifdef HAVE_USBHOST int ret; @@ -130,5 +185,66 @@ } #endif + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI2 + /* Get the SPI port */ + + message("nsh_archinitialize: Initializing SPI port 2\n"); + spi = up_spiinitialize(1); + if (!spi) + { + message("nsh_archinitialize: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + message("nsh_archinitialize: Successfully initialized SPI port 2\n"); + + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + message("nsh_archinitialize: Bind SPI to the SPI flash driver\n"); + mtd = m25p_initialize(spi); + if (!mtd) + { + message("nsh_archinitialize: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + return -ENODEV; + } + message("nsh_archinitialize: Successfully bound SPI port 0 to the SPI FLASH driver\n"); +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef CONFIG_NSH_HAVEMMCSD + /* First, get an instance of the SDIO interface */ + + message("nsh_archinitialize: Initializing SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + message("nsh_archinitialize: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + message("nsh_archinitialize: Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + message("nsh_archinitialize: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. I need to check to + * see if the STM32F4discovery SDC_ETH_extIO base board supports a GPIO to detect + * if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif return OK; } Only in nuttx-6.22/configs/stm32f4discovery/src: up_ostest.c diff -ur nuttx-6.22.orig/configs/stm32f4discovery/src/up_pwm.c nuttx-6.22/configs/stm32f4discovery/src/up_pwm.c --- nuttx-6.22.orig/configs/stm32f4discovery/src/up_pwm.c 2012-09-30 04:14:48.000000000 +0900 +++ nuttx-6.22/configs/stm32f4discovery/src/up_pwm.c 2012-10-28 14:42:26.000000000 +0900 @@ -57,13 +57,11 @@ /* Configuration *******************************************************************/ /* PWM * - * The stm32f4discovery has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this + * The stm32f4discovery extend base board has piezzo buzzer driven PWM devices * purpose: * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * PB8 / MC_TIM10_CH1OUT * - * FSMC must be disabled in this case! */ #define HAVE_PWM 1 @@ -72,15 +70,15 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32_TIM4 +#ifndef CONFIG_STM32_TIM10 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32_TIM4_PWM +#ifndef CONFIG_STM32_TIM10_PWM # undef HAVE_PWM #endif -#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +#if CONFIG_STM32_TIM10_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL # undef HAVE_PWM #endif @@ -138,5 +136,6 @@ return OK; } - +#else +# warning "PWM disabled." #endif /* HAVE_PWM */